1. Field of the Invention
The present disclosure relates to a liquid crystal display device and, more particularly, to an array substrate for a liquid crystal display device and a fabrication method thereof.
2. Discussion of the Related Art
In general, the driving principle of a liquid crystal display (LCD) device uses an optical anisotropy and polarization properties of liquid crystal. Liquid crystals have a thin, long structure, so they have orientation in an alignment of molecules, and the direction of the alignment of molecules can be controlled by intentionally applying an electric field to the liquid crystal.
Thus, when the direction of the alignment of molecules of the liquid crystal is adjusted, the alignment of molecules of the liquid crystal can be changed, and light is refracted in the direction of the molecular alignment of the liquid crystal by optical anisotropy, thus displaying image information.
Currently, an active matrix liquid crystal display (AM-LCD) (which will be referred to as an ‘LCD’, hereinafter) in which thin film transistors (TFTs) and pixel electrodes connected to the TFTs are arranged in a matrix form has come to prominence because of its excellent resolution and video implementation capabilities.
The LCD includes a color filter substrate (i.e., an upper substrate) on which a common electrode is formed), an array substrate (i.e., a lower substrate) on which pixel electrodes are formed, and liquid crystal filled between the upper substrate and the lower substrate. In the LCD, the common electrode and the pixel electrodes drive liquid crystal by an electric field applied vertically, having excellent characteristics of transmittance, aperture ratio, and the like.
However, the driving of liquid crystal by the electric field applied vertically is disadvantageous in that viewing angle characteristics are not good. Thus, in order to overcome the shortcomings, a method for driving liquid crystal by in-plane field has been newly proposed. The method for driving liquid crystal by in-plane field has excellent viewing angle characteristics.
In the in-plane switching mode LCD is configured such that a color filter substrate and an array substrate face each other, and a liquid crystal is interposed therebetween.
On the array substrate, a TFT, a common electrode, and a pixel electrode are formed on each of a plurality of pixels defined on the transparent insulating substrate.
Also, the common electrode and the pixel electrode are separated to be parallel on the same substrate.
The color filter substrate include black matrixes at portions corresponding to gate lines, data lines, and the TFTs on the transparent insulating substrate, and color filters are formed to corresponds to the pixels.
The liquid crystal layer is driven by an in-plane field of the common electrode and the pixel electrode.
In the in-plane switching mode LCD configured as described above, the common electrode and the pixel electrode are formed as transparent electrodes in order to secure luminance, but only portions of both ends of the common electrode and the pixel electrode contribute to improvement of the luminance due to the distance between the common electrode and the pixel electrode in terms of design and most regions block light.
Thus, a fringe field switching (FFS) technique has been proposed to maximize the luminance improvement effect. The FFS technique precisely controls liquid crystal to eliminate a color shift and obtain high contract ratio, implementing high screen quality compared with the general in-plane switching technique.
However, although the related art FFS mode LCD can implement a wide viewing angle in left and right viewing angles, as the size of the LCD is increased, the lateral viewing angle and upper and lower viewing angles are required to be further improved.
The related art FFS mode LCD will now be described with reference to FIG. 1.
FIG. 1 is a plan view of an array substrate of the related art LCD device.
As shown in FIG. 1, the array substrate for the related art LCD device includes a plurality of gate lines 17b extending in one direction and separated to be parallel on a substrate 11, a plurality of data lines 29c crossing the gate lines 17b and defining pixel regions at the crossings of the gate lines 17b and the data lines 29c; and a thin film transistor (T) provided at the crossing of the gate line 17b and the data line 29c and including a gate electrode 17a, an active layer (not shown), a source electrode 29a, and a drain electrode 29b. 
Also, a transparent pixel electrode 13a is disposed to be separated from the gate line 17b and the data line 29c on the entire surface of the pixel region, and a plurality of transparent common electrodes 39a having a bar-like shape are disposed at an upper portion of the pixel electrode 13a with an insulating film (not shown) interposed therebetween.
The pixel electrode 13a is electrically connected by a pixel electrode connection pattern 39b connected with the drain electrode 29b. 
Lateral ends of the plurality of common electrodes 39a having a bar-like shape are connected with the common electrode connection pattern 39c, and a portion of the common electrode connection pattern 39c is disposed to be parallel to the gate line 17b. 
Meanwhile, in case of exposing to form a contact hole 37 for connecting the pixel electrode 13a and the drain electrode 29b, an overlay margin M1 of about 2 μm is required between one end of each of the plurality of common electrodes 39a and the pixel electrode connection pattern 39b, and a short margin of about 4 μm is required between the pixel electrode connection pattern 39b and the edge of the side of the common electrode 39a, reducing the upper common electrode 39a, which leads to a reduction in the aperture ratio of the common electrode, an increase in the black matrix used for blocking light, and a reduction in transmittance.
A method for fabricating the array substrate for an in-plane switching (IPS) mode LCD device according to the related art configured as described above will be described as follows.
FIGS. 2A to 2O are sectional views taken along line II-II in FIG. 1 of the array substrate for an LCD device according to the related art.
FIG. 3 is a sectional view showing the process of fabricating the array substrate for an LCD device according to the related art, which explains a defective disconnection of a pixel electrode during an exposure process for patterning a common electrode.
As shown in FIG. 2A, a plurality of pixel regions including a switching region are defined on the transparent insulating substrate 11, an ITO layer 13 is deposited on the transparent insulating substrate 11 through sputtering, and then, a first photosensitive film 15 is applied on the ITO layer 13.
As shown in FIG. 2B, the first photosensitive film 15 is exposed and developed through a first masking process using photolithography to selectively pattern the first photosensitive film 15 to form a first photosensitive film pattern 15a. 
As shown in FIG. 2C, the ITO layer 13 is selectively patterned by using the first photosensitive film pattern 15a to form the pixel electrode 13a. 
Thereafter, the first photosensitive film pattern 15a is removed, a gate electrode metal layer 17 is deposited on the entire surface of the substrate including the pixel electrode 13a through sputtering, and a second photosensitive film 19 is coated thereon.
As shown in FIG. 2D, the second photosensitive film 19 is exposed and developed through photolithography so as to be selectively patterned to form a second photosensitive film pattern 19a. 
As shown in FIG. 2E, the metal layer 17 is selectively patterned by using the second photosensitive film pattern 19a as a mask to form a gate line (not shown) along with the gate electrode 17a. 
As shown in FIG. 2F, the second photosensitive film pattern 19a is removed, a gate oxide film 21, an amorphous silicon layer 23, and an amorphous silicon layer 25 including impurities are sequentially deposited on the entire surface of the substrate including the gate electrode 17a and the pixel electrode 13a, and then, a third photosensitive film 27 is coated on the amorphous silicon layer 25 including impurities.
As shown in FIG. 2G, the third photosensitive film 27 is exposed and developed so as to be patterned through a third masking process using photolithography to form a third photosensitive film pattern 27a. 
As shown in FIG. 2H, the amorphous silicon layer 25 containing impurities and the amorphous silicon layer 23 are selectively patterned by using the third photosensitive film pattern 27a as a mask to form an ohmic-contact layer 25a and an active layer 23a overlapping with the gate electrode 17a. 
Thereafter, the third photosensitive film pattern 27a is removed, a metal layer 29 is deposited on the entire surface of the substrate including the active layer 23a and the ohmic-contact layer 25a, and then, a fourth photosensitive film 31 is coated on the metal layer 29.
As shown in FIG. 2I, the fourth photosensitive film 31 is exposed and developed so as to be patterned through a fourth masking process using photolithography to form a fourth photosensitive film pattern 31a. 
As shown in FIG. 2J, the metal layer 29 is selectively patterned by using the fourth photosensitive film pattern 31a as a mask to form separated source and drain electrodes 29a and 29b and a data line (not shown). At this time, a portion of the ohmic-contact layer 25a exposed between the source and drain electrodes 29a and 29b is also removed to form a channel region of the active layer 23a. 
As shown in FIG. 2K, the fourth photosensitive film pattern 31a is removed, a protective film 33 is deposited on the entire surface of the substrate including the source and drain electrodes 29a and 29b, and then, a fifth photosensitive film 35 is coated on the protective film 33.
As shown in FIG. 2L, the fifth photosensitive film 35 is exposed and developed so as to be patterned through a fifth masking process using photolithography to form a fifth photosensitive film pattern 35a. 
Subsequently, the protective film 33 and the gate insulating film 21 are sequentially etched by using the fifth photosensitive film pattern 35a as a mask to form a contact hole 37 exposing portions of the drain electrode 29b and the pixel electrode 13a. 
As shown in FIG. 2M, the fifth photosensitive film pattern 35a is removed, an ITO layer 39 is deposited on the protective film 33 including the contact hole 37 through sputtering, and then, a sixth photosensitive film 41 is coated on the ITO layer 39.
As shown in FIG. 2N, the sixth photosensitive film 41 is exposed and developed so as to be patterned through a sixth masking process using photolithography to form sixth photosensitive film patterns 41a and 41b. At this time, the sixth photosensitive film pattern 41a is formed at an upper portion of the ITO layer 39 corresponding to a pixel electrode connection pattern region connecting a pixel electrode and a drain electrode, and the sixth photosensitive film pattern 41b is formed at an upper portion of the ITO layer 39 corresponding to a common electrode region.
As shown in FIG. 2O, the ITO layer 39 is selectively etched by using the sixth photosensitive film patterns 41a and 41b as masks to form a pixel electrode connection pattern 39b connecting the drain electrode 29b and the pixel electrode 13a, a plurality of bar-like common electrodes 39a, and a common electrode connection pattern 39c connecting the plurality of common electrodes 39a to each other.
And then, the sixth photosensitive film patterns 41a and 41b are removed, completing the process for fabricating the array substrate for an IPS mode LCD device according to the related art.
However, as described above, when the sixth photosensitive film is exposed to form the common electrode 39a and the pixel electrode connection pattern 39b, the sixth photosensitive film pattern 41c for forming the pixel electrode connection pattern is formed only at a portion of the contact hole 37 due to misalignment as shown in FIG. 3, exposing a portion of the ITO layer 39 in contact with the pixel electrode 13a at a lower portion of the contact hole 37.
Thus, with the portion of the ITO layer 39 exposed, when the ITO layer 39 is etched by using the sixth photosensitive film pattern 41c as a mask, the ITO layer 39 at a lower portion of the contact hole 37 is etched, the underlying pixel electrode 13a is also etched together as the ITO layer 39 at a lower portion of the contact hole 37 is etched, causing the pixel electrode 13a to be disconnected.
Thus, in the related art, in order to solve the problem of the disconnection of the pixel electrode 13a caused as the underlying pixel electrode 13a is also etched together when the ITO layer 39 at a lower portion of the contact hole 37 is etched, the sixth photosensitive film pattern 41a for forming the pixel electrode connection pattern is formed up to the vicinity of the common electrode region including the contact hole 37 region.
However, since the sixth photosensitive film pattern 41a for forming the pixel electrode connection pattern is formed up to the vicinity of the common electrode region including the contact hole 37 region, the area of the common electrode is reduced as much. Namely, when the ITO layer is exposed, an overlay margin M1 of about 2 μm or greater is required between one end of the plurality of common electrode and the pixel electrode connection pattern and a short margin of about 4 μm or greater is required between the edge of the side of the common electrode and the pixel electrode connection pattern, so the area of the common electrode is reduced to reduce the aperture ratio and transmittance.
Also, in the array substrate for an LCD device and the fabrication method thereof, the array substrate for an LCD device is fabricated through the six masking processes, namely, the first masking process for forming the pixel electrode, the second masking process for forming the gate electrode, the third masking process for forming the active layer and the ohmic-contact layer, the fourth masking process for forming the source and drain electrodes, the fifth masking process for forming the contact hole to connect the drain electrode and the pixel electrode; and the sixth masking process for forming the common electrode, so the number of fabrication processes are increased to lengthen time required for the fabrication process as much.